MSI Interrupt not working

[Altera_Forum]

Hi, 

I wrote a PCIe device driver. The driver is installed successfully. Interrupt is set to MSI. After installation, Power Enters D0 state. Interrupt enabled (MSI, MSEnable bit =1). Legacy Interrupt is disabled. There are two BARs (BAR0 - 1K, BAR2 - 64K). I tried two Altera PCIe projects (one with ST interface, the other is DMA interface). The ST interface will be able to write BAR0 and read back with the same value as follows:   0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010   0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011   0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013   0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017   0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F The BAR2 reads different data after writing:  Write: 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010   Read: 9003 E590 04E5 0304 F880 FFF8 08FF 8008 8863 EB88 0CEB 630C 0001 0000 1000 0110  Write: 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022   Read: 9003 E590 16E5 0316 0001 0000 1A00 011A 0000 0000 1E00 001E 0000 0000 2200 0022  I believe data is updated by FPGA.  For the DMA project, both BAR0 and BAR2 read different data after writing.  I guess the FPGA is updating the memory and sending data to PC.  But the interrupt routing is not called a single time.  At device add routine: the configuration MSI CAP :05 78 84 00 00 00 00 00 00 00 00 00 00 00 00 00 At the event call : DeviceD0Entry() the configuration MSI CAP is : 05 78 A5 00 0C F0 E0 FE 00 00 00 00 B4 49 00 00. This seems confirmed that MSI is enabled, Vector is set.  Thank you, Tiger

[Altera_Forum]

I set the PCI express Avalon MM Bridge registers at 0x0050 (PCI Express interrupt Enable Register) to 0x0FF0000. But the number is not taken.  

 Was the register right? how to enable the interrupt?  Thanks, Tiger

[Altera_Forum]

To enable MSI interrupts, ensure to enable the CRA port.  

Software driver at host PC also needs to set the MSI enable bit and Interrupt Disable bit. 1. Set MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register. 2. Set Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to disable legacy interrupt. 3. Set bit[1] (Memory space) and bit[2] (Bus Master) of Command Register at configuration space offset register 0x4 to enable the ability to  generate MSI message.