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Altera_Forum
Honored Contributor I
805 Views

verifying tranceiver connections

i have a custom design where i am using 4 transceivers on cyclone 5 GX device which can be seen in the attached schematic. The 4 transceivers all go to sfp modules. one will be Ethernet connectivity, two board to board daisy Chainning and the other transceiver will be spare. 

 

i am still at hardware design stage and using quartus to test my pinouts. i haven't used the transceivers before on any previous designs so iam a bit unclear on what connects where. 

i have a piece of code which was written by another engineer that has a working qsys Ethernet design which i have linked this to my top level . 

 

With the reference clk REFCLK0P and REFCLK0N i send the signals through a LVDS buffer to produce a 125MHz clock which i connect to the top level QSYS connection "ethernet_pcs_ref_clk_clock_connection_clk" . 

 

when running the fitting, the design fits fine. now i want try and get 2 Ethernet transceivers working so i added another copy of the qsys Ethernet subsystem and now i have 2 reference clocks called "ethernet_pcs_ref_clk_clock_connection_clk" and "ethernet_1_pcs_ref_clk_clock_connection_clk". 

 

when i try running fitting an error apears called 

 

Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 Channel PLL(s)) 

 

i tried a different a approach by connecting the pcs_ref_clk_clock_connection_clk signals to a 125MHz pll driven by a 50 MHz system clock. 

 

This still doesn't work and also now that i have removed the clock driven by REFCLK0P and REFCLK0N ( through the lvds buffer) these two signals do not have any connection on my too level design? 

any help with the questions below would be greatly appreciated 

 

1) checking my connections and 

2) helping me get ethernet working on all 4 channels would be great, 

3) last what are the REFCLK0P and REFCLK0N clocks used for? 

.
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Altera_Forum
Honored Contributor I
25 Views

I suggest you to read the transceiver chapter on your device handbook and look into the xcvr_user_guide. 

 

Anyway it seems that you configure your xcvr ip to use a cmu pll as tx pll. 

This mean that you use another xcvr cdr as tx pll. 

To your pinout this imply that you have to leave a xcvr receiver not use in the middle of a triplet (channel 1 or 4 of a six pack). 

 

If you add other channels at same datarate you can reuse the same tx pll also for the others. 

In order to have this working you've to satisfy some rules (pll powerdown and phy resets to be driven by same signals and you have to give an assignment to say that all those tx channels are part of same xcvr group). 

 

Note that for ethernet you could have used alse a fpll as tx pll and in this case you do not need to leave any space between the xcvrs. 

 

Last but not least you need to instantiate a xcvr reconfiguration controller and all channels on the same triplets must use the same reconfig controller. 

I suggest you to use one per side or one for the whole fpga. Pay attention that xcvr phy ip tell you how many reconfig controller interfaces they need. 

I suggest you to split them in xcvr rcfg ip in case you use one for multiple phys: it will let your connections be easier.  

 

I think that what I wrote will have no sense for you until you do not study xcvr from handbook or attend some online training (altera web site is full of them and they are free)!
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