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Altera_Forum
Honored Contributor I
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UniPHY DDR3 controller for arriaVGz

Hi, 

I recently generated a DDR3 controller IP core with UniPHY using quartus 14.1. The master side of the core is 256 bits wide (byte enable width is 32) and slave is 64 bits. I have verified the write, read with multiple burstlengths using the same core. But I am currently facing issues with the byte enable functionality of the core. Since the core I generated is for x4 configuration, each byte disabled operation involves a read from the specified location and write back with the requires bytes modified. I am writing 8 consecutive data to the slave followed by 4 consecutive modification with byte enables 0xf0000000, 0x0f000000, 0x00f00000 and 0x000f0000. When reading back from the ddr3 model generated by the tool i am finding the the first two data has been modified as per the byte enable signal given, but the third data has been modified with fourth byte enable signal. 

 

If I try to do 8 consecutive writes with byte enable the simulation will stop at the 7th write command with the ready signal pulled low (avl_ready) and reading back from the device is not happening. 

 

I have attached the code i am using and the initialization data for write_data, byte_enable, received data and address. 

 

Please let me know what the issue is as soon as possible.
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