Hello.
I'm trying to simulate project with getting data from OnChipFlash.
I'm using the Lite edition of Quartus 17.0.2 and ModelSim - INTEL FPGA STARTER EDITION 10.5b.
I create testbench file to simulate the project. I start the simulation using "Tools -> Run Simulation Tool -> RTL Simulation".
When the simulation starts, I get following error on the ModelSim output:
** Error: (vsim-3033) c:/intelfpga_lite/16.1/projects/dac+nios_ltc1668+ad5791_fsm/db/ip/onchipflash/submodules/altera_onchip_flash.v(305): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /AC_main_tb/main_inst/sin_data/onchip_flash_0 File: c:/intelfpga_lite/16.1/projects/dac+nios_ltc1668+ad5791_fsm/db/ip/onchipflash/submodules/altera_onchip_flash.v
When I comments the OnChipFlash module everything works well, but without extracting data from flash.
File altera_onchip_flash_block.v do not opened, because is encrypted file.
I find similar post on forum:
I tried to perform the actions as written in the post above with the substitution of my names:
1) Open the qsys files, generate the simulation model, generate -> generate hdl
2) Open modesim, cd to directory where the msim_setup.tcl
source msim_setup.tcl
3) ld
4) open the msim_setup.tcl and modify the top level from "OnChipFlash" to "AC_meas_tb"
6) add the following lines under vlog in "alias com" section, at the end, in this order:
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/main.v"
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/AC_meas_tb.v"
7) ld again.
I get following error:
Error: (vlog-7) Failed to open design unit file "./..//main.v" in read mode.
# No such file or directory. (errno = ENOENT)
If I start simulation using "Tools -> Run Simulation Tool -> RTL Simulation" I get error Error: (vsim-3033) .....altera_onchip_flash.v(305): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
At this point, any help would be greatly appreciated, or workaround as well.
Thanks, Aleksey
You make the AC_meas_tb as the testbench. Can you check inside the AC_meas_tb.v files, what is your module name there? currently, the tools are complaining the testbench issue.
連結已複製
Thanks for answer.
You are right, the problem is with the paths.
I changed the lines as follows:
eval vlog $ USER_DEFINED_VERILOG_COMPILE_OPTIONS $ USER_DEFINED_COMPILE_OPTIONS "$ QSYS_SIMDIR /../../ main.v"
eval vlog $ USER_DEFINED_VERILOG_COMPILE_OPTIONS $ USER_DEFINED_COMPILE_OPTIONS "$ QSYS_SIMDIR /../../ AC_meas_tb.v"
Now all modules are compiled without errors after command:
source msim-setup.tcl,
ld,
but an error is thrown at the end:
# vsim -t ps -L work -L work_lib -L onchip_flash_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver AC_meas_tb
# Start time: 09:02:11 on Feb 27,2020
# ** Error: (vsim-3170) Could not find 'AC_meas_tb'.
# Searched libraries:
******
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./AC_meas_NIOS_run_msim_rtl_verilog.do PAUSED at line 24
I do not understand which "AC_meas_tb" the simulator does not find.
PS If I start RTL simalation from Qaurtus I get error "Error: (vsim-3033): Instantiation of 'altera_onchip_flash_block' failed".
Module name in AC_meas_tb.v file is "AC_meas_tb". It seems to be right.
PS If I start RTL simalation from Qaurtus I get error "Error: (vsim-3033): Instantiation of 'altera_onchip_flash_block' failed".
do not use this method, this method is not for platform designer usage.
Do I understand you correctly that running a simulation through Quartus (Tools-> Run Simulation Tool-> RTL Simulation) is possible only if there are no IP components? As soon as the IP component is included in the project, the start of the simulation is possible only through manually editing a file "msim_setup.tсl and further execution of the LD command. The only way?
Yes, some of the IP component use platform designer format. If use megawizard/megafunction it is still fine.
Anyway, I look into your .v files, it
AC_main_tb which is not AC_meas_tb, you may need to change it.
Thanks a lot KennyT_Intel!
You are a very attentive, but I am not at all! If it weren’t for you, I wouldn’t notice the difference between MAES and MAIN in "AC_xxxx_tb", because they are so similar among a huge number of letters!
KennyT_Intel, I ask you to answer one more question:
If I modify a file in the project, then to restart the simulation with the new data, I first stop the simulation "quit-sim" and recompile with the commands "source msim_setup.tcl" and "LD", but modelsim gives a lot of errors on each external module used by top-level file MAIN.v:
# Loading work.main
# ** Error: (vsim-3033) ./../../../main.v(198): Instantiation of 'receiving_from_PC' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /AC_meas_tb/main_inst File: ./../../../main.v
etc.
If I quit from ModelSim and start it again, do all operations described above, simulation start again normal.
How restart simulation without reopen ModelSim?
It didn’t help, the same error, after commands "restart -f -> source msim_setup.tcl -> ld":
# Loading work.main
# ** Error: (vsim-3033) ./../../../main.v(198): Instantiation of 'receiving_from_PC' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /AC_meas_tb/main_inst File: ./../../../main.v
etc.
Here is what I noticed.
1) When I start ModelSim from Quartus I get an error. Next, with the CD commands, I go to the msim_setup.tcl file, execute the source and ld commands. The simulation starts. Restarting the simulation fails with the above error.
2) When I start ModelSim from the Windows START menu, with the CD commands I go to the msim_setup.tcl file, I execute the source and ld commands, the simulation does not start, but ends with the same error as when restarting.
That is, the simulation only works when starting ModelSim from Quartus and then writing commands on its command line.
Why does the simulation not work when starting ModelSim from the START menu of Windows and how to restart the simulation all the same without reopening ModelSim?
This seems to be the setting of the modelsim got some problem. The modelsim of the setting is modelsim.ini, what you can do is try to backup this file and let the modelsim recreate it from scratch.
Hello KennyT_Intel.
I deleted the modelsim.ini file, ModelSim recreated it exactly the same and this did not solve the problem.
After a little thought, I decided to add lines to the "alias com" section with modules on which the ModelSim gives errors:
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../../receiving_from_PC.v"
etc.
This solve the problem.
Thanks!
Again the problem.
Data from flash memory is not retrieved, data is always in logical 1.
Modelsim writes the following in log:
# ** Warning: (vsim-3017) ./../submodules/altera_onchip_flash.v(297): [TFMPC] - Too few port connections. Expected 18, found 17.
# Time: 0 ps Iteration: 0 Instance: /AC_meas_tb/main_inst/sin_data/onchip_flash_0/altera_onchip_flash_block File: nofile
# ** Warning: (vsim-3722) ./../submodules/altera_onchip_flash.v(297): [TFMPC] - Missing connection for port 'bgpbusy'.
# ** Warning: (vsim-3017) <protected>(<protected>): [TFMPC] - Too few port connections. Expected <protected>, found <protected>.
# Time: 0 ps Iteration: 0 Protected: /AC_meas_tb/main_inst/sin_data/onchip_flash_0/altera_onchip_flash_block/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: nofile
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
These are the only compilation warnings.
All data is protected. Therefore, there is no retrieval of them?
I thought that the problems were only with the simulation, since in addition to the data, all other signals are formed as it should, judging by the simulator.
After programming, the project works the same way - reading a flash always returns FFFFFFFF.
After I started the simulation of the project with the OnchipFlash module used (thank you for your help), the simulator shows that FFFFFF is always returned from the flash. Having programmed the project, I was convinced of it, observing the data on an oscilloscope.
I searched the Internet for an example of working with Flash memory, thinking that there was a mistake somewhere in my project and therefore FFFFF was always read from Flash. On FpgaCloud, I found a project like this:
I started the simulation and saw that FFFFF is always read from Flash. This project was created by Altera (Intel), I am sure that there is no error in it.
Why is FFFFF always read from Flash?
PS I am using Quartus 17.0.
