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Multiple packets in 256-bit PCIE endpoint

Honored Contributor II



I want to use stratix V 256-bit pcie end point in my design. Is it possible that the endpoint outputs 2 mem read/write TLPs in the same cycle??? 


In other words, In 256-bit end point we have a two bit st_avalon_sop and st_avalon_eop signal. Is it possible that the endpoint asserts both sop bits or both eop bits in the same cycle? 


Since a read tlp only occupy 3 DWs so should I need to implement the support to handle two memory read/write TLPs in the same cycle 


Thanks in advance
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