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Newbie question: Quartus Web Edition, Altera IP?

Honored Contributor II



I got one of the nice DE series dev boards, I just downloaded Quartus II Web Edition, and I am just starting to learn about Altera FPGAs. One question that I have been left wondering about is as follows: Exactly what kind of "IP" or basic building blocks are free and fully included in the Quartus Web Edition?  


I assume I can place a logic gate on the schematic description "for free". 


On the other hand, in Qsys, I can add a QDR II+ SRAM controller component to my system. Not that I can actually use that, I am just playing around with the GUI. However, I don't get any warnings about licensing when doing this, yet it seems to me that this is one component that I would eventually have to buy a license for. When and how am I going to find out that I can't complete something that started to do, because it will require a license? 


I simply want to start out doing things that I can actually fully implement without any licensing or timeout issues. It is not clear to me which things will work (i.e., everything I can place on a schematic editor?) and which things will time out (i.e., anything that I build in Qsys with the Web Edition?). 


I just want to educate myself for a few months, using the Quartus Web Edition exclusively (and not the 30 days trial of Full Quartus) to build some simple non-expiring FPGA functionality. 


Please advise.
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Honored Contributor II

First if you have any license installed, it will show up in Tools > License Setup. The version column should tell you when the corresponding license will expire (although Licenses never expire, but I never fully understood how to make the difference). 

Then if you compile a project with an unlicensed IP (or an IP with an expired license), you will see that the compiled image is placed in a file ending with _time_limited.sof instead of the regular .sof. You will also get a warning message each time you configure the FPGA, so it's hard to miss ;) 

In that case you can still run your design on the FPGA, but in evaluation mode. The USB blaster needs to be connected to the FPGA for as long as you want to run your test, and you wonæt be able to flash your project.
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