PCI Avalon-MM Multi-master arbitration

[Altera_Forum]

Hi, 

 I want to do a qsys system with two "Avalon-MM Stratix V Hard IP for PCI Express" which need to access the same Avalon-MM slave.  Anyone know a solution for the arbiter between those two master? If it could help, both master won't be communicating at the same, so in a way, I need more an avalon mux then an arbiter.  I have already read multiple thread about this, but none represent my system. Each "Avalon-MM Stratix V Hard IP for PCI Express" have it's own master interface as well as it's own master clock output. So I need an arbiter with multiple slave+clock interface and only one master+clock output interface. I saw the MPFE module but it doesn't fit this design.  I tried to connect both master interface to my slave, export each master clock, do a clock mux in the logic external to qsys then send this clock to the qsys with a clk_src. But this solution gives me a lot of timing issue and sometimes the reading of my slave register doesn't work.  Best regards, Jerome

[Altera_Forum]

You don't need an explicit mux, just connect the slave to both Masters and the QSYS fabric takes care of it. Same happens if you say connect one slave to both BAR0 and BAR1 on a single master.

[Altera_Forum]

Hi, thanks for your answer. If I connect both master avalon bus port to my slave, what about the clock? My slave requires a clk_in and a reset source. Can I feed any free running clock to that slave and the avalon fabric will insert buffer?

[Altera_Forum]

The master that is *not* providing the clock input will automatically have a clock crossing adapter inserted by QSYS. I tried to inline a picture but the forum won't accept it.  

 https://drive.google.com/file/d/0b5drao0__dlkv2dzwfhaawo1tdq/edit?usp=sharing  You can re-create the example in Qsys very quickly. Do File -> "New system". Delete the clock input block. Add two "Avalon-MM StatixV Hard IP for PCI Express" (avmm) cores. In the wizard only enable BAR0 as 32-bit then finish. Add "On-Chip Memory (RAM or ROM)". Couple up the onchip memory to avmm0 coreclkout, nreset_status and Rxm_BAR0. Now also couple onchip memory to avmm1 Rxm_BAR0. Add the cra ports on respective avmm BAR ports. Export all the refclock, transciever reconfig etc. Change base address of onchip to be 0x4000 on both core's BAR0.  The Avalon Memory Mapped Slave is actually actually two networks, command and response. You will see this if you run System -> Show System with QSYS Fabric Components. It's pretty overwhelming to start. There are two "Avalon-ST Handshake Clock Crosser" components inserted towards the end. These handle the clock crossing between the pcie coreclkout domains. One is for commands (avmm1 -> avmm0), the other for responses (avmm0 -> avmm1).  The usage of these 'implicit' crossers is adequate on a small system. If you add lots of slave devices the QSYS fabric gets large. For instance 2 masters, 3 slaves requires 6 Handshake Clock Crossers (3 pairs). You get an extra pair for each foreign clock domain master to slave connection. In this case it's better to put all the slaves behind a single explicit "Avalon-MM Clock Crossing Bridge". You then get a single clock crosser pair between the foreign master's clock domain and the bridge.  It's easy to create lots of clock crossers and they can be hard to find if you didn't intend to make them. I think the 13.1 QSYS tool is better at showing this.

[Altera_Forum]

Ok thanks, didn't knew there was so much magic around the QSYS system. Just before I saw you answer, I added an "Avalon-MM Clock Crossing Bridge" after each of my master. So all slave share a common free running clock with the other side of the clock crossing bridge. I have many slaves (I specified only one in my first post, but that was only to simplify the problem), so I think I will keep the "Avalon-MM Clock Crossing Bridge" like you suggested. 

 Best regards, Jerome