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Altera_Forum
Honored Contributor I
710 Views

PCI express reference design doesn't complete

I downloaded the reference design for PCI express to external memory reference design (AN431). 

 

I unzipped it and ran the do runtb.do script and the simulation ran through to 400us and then stopped. The transcript is attached. 

 

 

The last thing it does is wait for a competion that never seems to come. I  

have ran it beyond 1ms and still nothing happens. I would expect it  

to carry out DDR2 writes. 

 

Has anyone else seen this. 

 

I am using modelsim-altera 6.5b 

 

thanks in advance
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Altera_Forum
Honored Contributor I
43 Views

After debugging the reference design (Thanks Altera :rolleyes: ). I believe the issue is to do with the data word length counter in the rx_pcie.v file within the application section. 

 

On line 449 it says  

 

always @(Rx_St_Sop) 

rx_modlen = rx_dwlen; 

 

I changed this to  

 

always @* 

rx_modlen = rx_dwlen_reg;//rx_dwlen; 

 

The rx_dwlen changes as the data goes through the RX_Data_A registers. Although the process should only be sensitive to the pulse of "Rx_St_Sop" it seems to follow the rx_dwlen changing value. This means that the burst size out to the DDR memory becomes 1. The read following it is one as well. the simulation fails because the data does not match with what it was expecting. i.e. 16 dwords. 

 

Using the "rx_dwlen_reg" holds the correct value allowing the simulation to work as it should. 

 

Chris
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