FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

PCIe IP Core- MSI-x interrupt receiving issue.

Altera_Forum
Honored Contributor II
925 Views

Hello All, 

 

I am facing some issue in receiving MSI-x interrupt.I am using reference design provided at altera_wiki to test MSI-x for Stratix V FPGA.I am not able to receive MSI-x interrupt at driver level.I checked that pcie_irq component used to store vector address and data address for different MSI-x interrupt generates Avalon Master write request when it receives any interrupt i.e TXs port of the PCIe IP Core receives Avalon write request.But linux driver doesn't get any interrupt event.I have enabled MSI-x interrupt and disable legacy interrupt at driver level.I have also enabled Master Enable bit for Command register in configuration space of the PCIe IP Core. 

 

So would someone please help me to resolve this issue or provide me working design to test MSI-x interrupt? 

 

Thanks in advance, 

 

Krupesh 

(http://www.alterawiki.com/wiki/handling_pcie_interrupts) - See more at: https://mysupport.altera.com/alteraservreq/openservreqdetail.html?srno=11180263&srrowid=1-dqj04j#sthash.hizosrst.dpuf 

(http://www.alterawiki.com/wiki/handling_pcie_interrupts) - See more at: https://mysupport.altera.com/alteraservreq/openservreqdetail.html?srno=11180263&srrowid=1-dqj04j#sthash.hizosrst.dpuf 

 

(http://www.alterawiki.com/wiki/handling_pcie_interrupts) - See more at: https://mysupport.altera.com/alteraservreq/openservreqdetail.html?srno=11180263&srrowid=1-dqj04j#sthash.hizosrst.dpuf 

 

(http://www.alterawiki.com/wiki/handling_pcie_interrupts) - See more at: https://mysupport.altera.com/alteraservreq/openservreqdetail.html?srno=11180263&srrowid=1-dqj04j#sthash.hizosrst.dpuf 

 

(http://www.alterawiki.com/wiki/handling_pcie_interrupts) - See more at: https://mysupport.altera.com/alteraservreq/openservreqdetail.html?srno=11180263&srrowid=1-dqj04j#sthash.hizosrst.dpuf) . I am using Cyclone V FPGA and  

 

 

 

(http://www.alterawiki.com/wiki/handling_pcie_interrupts) - See more at: https://mysupport.altera.com/alteraservreq/openservreqdetail.html?srno=11180263&srrowid=1-dqj04j#sthash.hizosrst.dpuf 

 

 

 

 

 

 

 

 

 

(http://www.alterawiki.com/wiki/handling_pcie_interrupts) - See more at: https://mysupport.altera.com/alteraservreq/openservreqdetail.html?srno=11180263&srrowid=1-dqj04j#sthash.hizosrst.dpuf 

(http://www.alterawiki.com/wiki/handling_pcie_interrupts) - See more at: https://mysupport.altera.com/alteraservreq/openservreqdetail.html?srno=11180263&srrowid=1-dqj04j#sthash.hizosrst.dpuf
0 Kudos
0 Replies
Reply