PCIe Legacy Interrupts Not Happening

[Altera_Forum]

I have a Cyclone V design built with Qsys (Quartus II 13.0 SP1). The Qsys module has an Avalon-MM bus, a C5 HIP PCIe core and some other blocks connected to PCIe BARs (all 32-bit non-prefetch). The PCIe is a single DW completer, Gen1 x1 and using 62.5MHz clock from the PCIe, for Avalon. Pretty basic config. 

 I'm trying to use Legacy interrupts. The INTx port is exported out of the Qsys module and the interrupt input signal comes from a custom interrupt controller. I can control the interrupt signal at will, I see it going high/low (confirmed by bringing the signal out of the FPGA) but I don't see a corresponding change in the PCIe Status Register. (Should I?)  In addition, I don't see eny change to the interrupt acknowledge signal. There should be a pulse appearing when the INTA TLP is sent out by the PCIe core. Using some windows utilities also show that not interrupt is seen coming from the PCIe core.  I checked a number of things. The Command Register shows interrupt enabled (i.e. not disabled). MSI is not enabled. I even tried the "Auto enable PCIe interrupt (enabled on power-on)" option ticked, but no difference. Meanwhile, I have absolutely no problem reading/writing the BAR areas. :confused:  I've read through many interrupt related messages on this forum and elsewhere and not many sounded similar and even the ones that did, are supposed to have been fixed by earlier versions of Quartus.  I must be missing something basic. Has anybody seen anything similar? Do you have a similar design where you saw Legacy Interrupts working? Any advice on what to check for?  Any helping comments will be appreciated, thanks!  Sandor

[Altera_Forum]

Legacy interrupts are running now. There was a problem with the value of a parameter called "CG_ENABLE_ADVANCED_INTERRUPT" in one of the Qsys generated files. 

It's still being investigated by Altera but I thought I throw a clue :-) in case somebody else has similar problems.

[Altera_Forum]

--- Quote Start ---  Legacy interrupts are running now. There was a problem with the value of a parameter called "CG_ENABLE_ADVANCED_INTERRUPT" in one of the Qsys generated files. It's still being investigated by Altera but I thought I throw a clue :-) in case somebody else has similar problems.  --- Quote End ---    Hello, It seems to me that I have the similar problem, I can not see generation of legacy interrupts on my host PC. Do you have any details -> what did you need to change to enable legacy interrupts for you ? Could you please share your solution ?  Thank you.  Lukas

[Altera_Forum]

Sure, Lukas! 

 I have a Qsys subsystem inside my design which contains the PCIe core. Inside that, the altpcie_cv_hip_avmm_hwtcl submodule has a number of parameters/generics. The parameter CG_ENABLE_ADVANCED_INTERRUPT exists in altpcie_cv_hip_avmm_hwtcl and quartus should automatically set it when you select legacy interrupt but it doesn't. You have to manually add the generic both to the component declaration and the generic mapping at the instantiation, in your Qsys module.  Insert into the component declaration: CG_ENABLE_ADVANCED_INTERRUPT : integer := 0;  Generic mapping: CG_ENABLE_ADVANCED_INTERRUPT => 1,  I'm guessing you are using VHDL at the top level of your Qsys design. I think people using Verilog at the top level don't have this problem.  Altera's promised to fix this in a future version of Quartus.  I hope this was the problem in your case too and you can fix it, with the above mod.  Sandor

[Altera_Forum]

--- Quote Start ---  Sure, Lukas!  I have a Qsys subsystem inside my design which contains the PCIe core. Inside that, the altpcie_cv_hip_avmm_hwtcl submodule has a number of parameters/generics. The parameter CG_ENABLE_ADVANCED_INTERRUPT exists in altpcie_cv_hip_avmm_hwtcl and quartus should automatically set it when you select legacy interrupt but it doesn't. You have to manually add the generic both to the component declaration and the generic mapping at the instantiation, in your Qsys module.  Insert into the component declaration: CG_ENABLE_ADVANCED_INTERRUPT : integer := 0;  Generic mapping: CG_ENABLE_ADVANCED_INTERRUPT => 1,  I'm guessing you are using VHDL at the top level of your Qsys design. I think people using Verilog at the top level don't have this problem.  Altera's promised to fix this in a future version of Quartus.  I hope this was the problem in your case too and you can fix it, with the above mod.  Sandor  --- Quote End ---     Hello Sandor,  thank you very much for your reply (event Altera support redirected me to your post :)). I also have QSYS subsystem in my design with altpcie_cv_hip_avmm_hwtcl submodule. And yes, I'm using VHDL at the top level of my Qsys design. I tried to perform changes you suggested (you were right, those parameters were not set/used in VHDL generated code) but despite that I was not successful. I can not receive legacy nor msi interrupts.   What I find strange when accessing CRA is that even if I write to enable interrupt register http://www.altera.com/literature/ug/ug_c5_pcie.pdf#page=167 -> eg. 0xFFFFFFFF and then I try to read the value back I read only zeros. It seems to me that I can read only zeros from CRA. Did you have similar experience ? Reading/Writing from other components on the same BAR over PCIe is no problem.  Please let me know if you have idea.  Thank you very much.  Best regards Lukas

[Altera_Forum]

Hello, sandord, thank you for your help. Finally, I solved my problem in this thread: http://www.alteraforum.com/forum/showthread.php?t=42711 or http://www.altera.com/support/kdb/solutions/rd03062014_662.html 

 Thank you !  Lukas

[Altera_Forum]

Hi Lukas, 

 I'm glad you managed to resolve your problem and I appreciate the additional information you posted. My advice was for legacy interrupts only but that's all I needed in my design, at the time.  Sandor