PCIe implementation in Cyclone IV

[Altera_Forum]

Hi friends, 

 I try to implement the Hard IP of PCIe in the Cyclone IV Dev Kit and i have a problem with the application layer, i don't know if i need to implement a nios to master the avalon interface or just a DMA ?  and if i want to made request from the FPGA to the PC how can I do it ??  do you have any idea about these questions ??  thnx :)

[Altera_Forum]

you can refer to the altera website for detail information 

http://www.altera.com/support/ip/interface-protocols/ips-inp-pcie.html?gsa_pos=10&wt.oss_r=1&wt.oss=pcie

[Altera_Forum]

thnx Peli, 

 i have already refer to this document but the manuals don't contain enough information :( :(  i don't know if the PCIe can be a master or it need a master ?? the same for the avalon bus ??  thnx friends