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Altera_Forum
Honored Contributor I
747 Views

PCIe implementation in Cyclone IV

Hi friends, 

 

I try to implement the Hard IP of PCIe in the Cyclone IV Dev Kit and i have a problem with the application layer, i don't know if i need to implement a nios to master the avalon interface or just a DMA ? 

 

and if i want to made request from the FPGA to the PC how can I do it ?? 

 

do you have any idea about these questions ?? 

thnx :)
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2 Replies
Altera_Forum
Honored Contributor I
37 Views

Altera_Forum
Honored Contributor I
37 Views

thnx Peli, 

 

i have already refer to this document but the manuals don't contain enough information :( :(  

i don't know if the PCIe can be a master or it need a master ?? 

the same for the avalon bus ?? 

 

thnx friends
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