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JET60200
New Contributor I
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PCIe "Asynchronous Clock" design on A10 FPGA

Hi,

Is there any example design for PCIe HIP that uses asynchronous clock as pcie reference clock in A10 fpga ?

Generally PCIE HIP is required to use the 100 MHz reference clock from the Host PCI Express Connector, which is named as "synchronous clock".   If PCIe uses the 100Mhz on-board reference clock which is "asynchronous clock" system as I know.

 

On our A10 board, we need use that " 100Mhz on-board reference clock from GPS locked Oscillator " ,  where can we find the ref design example ?

 

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2 Replies
45 Views

Hi,


Do you mean to connect the refclk pin to internal FPGA generated clock? The input reference clock, refclk, must be stable and free-running at device powerup for a successful device configuration.


Thanks

Best regards,

KhaiY



28 Views

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


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