PCS bonding channels must be locked in ascendning and continous order.

[EMOEN]

Hi,

I am currently trying to compile the "Intel FPGA HDMI IP" for an Achilles Arria 10 Instant Dev kit. I am using the Inrevium HDMI 2.0 FMC card. After filling in the pinout i get the following error:

Error (13118): PCS bonding channels must be locked in ascending and continuous order. The following channels fmcb_dp_c2m_p[0] fmcb_dp_c2m_p[1] fmcb_dp_c2m_p[2] fmcb_dp_c2m_p[3] use PCS bonding, but are not constrained ascending order. Modify your assignments in the Assignment Editor to lock the PCS channels in ascending and continuous order.

From UG-01143: Intel® Arria® 10 Transceiver PHY User Guide i do kind of understand why the error occurs but i havent been able to find a way to solve it. Any tip or hint leading me in the right direction is much appreciated.

Kind Regards,

Espsea

[Deshi_Intel]

Hi,

Arria 10 Transcevier (XCVR) bank typically has 6 channel [5:0] in a bank.

PCS bonding channels must be locked in ascending and continuous order

• means that all the 4 HDMI channels must be stick together side by side without a gap in between the channels
• ok example : assign 4 HDMI channels = XCVR [3:0]
• ok example : assign 4 HDMI channels = XCVR [5:2]
• not ok example : assign 4 HDMI channels = XCVR [4:2] + XCVR [0]

I hope I clear your doubt

Thanks.

Regards,

dlim

[EMOEN]

Hi,

Thank you for the reply!

I am using the following pinout which corresponds to the following

transceiver channels (according to manual from ReflexCES):

fmcb_dp_c2m_p[0] -> PIN_F32 -> Transceiver TX bank 1F lane 3

fmcb_dp_c2m_p[1] -> PIN_H32 -> Transceiver TX bank 1F lane 2

fmcb_dp_c2m_p[2] -> PIN_C34 -> Transceiver TX bank 1F lane 1

fmcb_dp_c2m_p[3] -> PIN_E34 -> Transceiver TX bank 1F lane 0

It does look like the channels are in a continous order in the Tranceiver TX 1F bank.

Regards,

Espsea

[Deshi_Intel]

Hi Espsea,

Your location pin placement looks fine. Attached is HDMI example design pin placement for another Arria 10 GX FPGA. You can see the HDMI pin placement is more or less alike.

Maybe you can try double check again the following

• make sure you select the correct Arria 10 FPGA device part number in Quartus project
• Ensure nothing wrong with your Quartus project pin assignment setting, HDMI RX channel is configured correctly as well
• Ensure transceiver refclk is using same refclk from same transcevier bank if possible

Feel free to also generate HDMI example design from Intel FPGA HDMI IP to cross check the pin setting with your project.

If you still can't find the fitter problem, then feel free to archived your Quartus project into *.qar file and share with me. Let me know which Quartus version that you used then I can help to review your design HDMI pin setting as well.

Thanks.

Regards,

dlim

[EMOEN]

Hi,

thank you for the reply.

I have tried your tips but i have not been able to

compile the design.

I am using the ReflexCES Achilles Instant Devkit with a Arria 10: 10AS066H2F34I1HG

I have attached the project, i would be grateful if you could take a look.

I am using Quartus Prime Pro Edition 20.1

This is the manual for the FMC card i am using: https://solutions.inrevium.com/products/pdf/TB_FMCH_HDMI4K_HWUserManual_2.04.pdf

Kind Regards,

Espsea

[Deshi_Intel]

sure, let me take a look at your design.

[Deshi_Intel]

HI Espsea,

After reviewing your design and compared with HDMI example design again, I found out your design HDMI pin placement is in DESCENDING order, not in ASCENDING order as required by PCS bonding. Attached is the diagram showing you the difference

That's explain why fitter compilation failed.

I have tested. Once you reverted your design HDMI pin placement from descending order back to ascending order then fitter compilation will pass.

Thanks.

Regards,

dlim

[Deshi_Intel]

HI Espsea,

I have not hear back from you for sometime.

Hopefully my earlier explanation is clear to you.

For now, I am setting this case to closure.

Feel free to post new forum thread if you still have new enquiry in future.

Regards,

dlim