Question about Transceiver Native PHY Intel Arria 10 FPGA IP

[BXia]

Hi,

We are using the Transceiver Native PHY Intel Arria 10 FPGA IP.

We configured two RX PHY for the same Arria 10 FPGA device, one is 20bits (see the attached picture 20bits.jpg) and another one is 16bits (see the attached picture 16bits.jpg).

The 20bits RX PHY works without problem, but frequently the PLL lock signal of 16bits RX PHY is low, it can't be locked, as shown in picture PLL_lock_signal.jpg, you can see the signal with blue color.

Are there any special considerations when we configuring it to 16bits RX PHY?

Thanks in advance.

[BXia]

Hi @intel

Could you look into this case and share any advice?

Thanks.

[Ash_R_Intel]

Hi,

Can you share the piece of your design Quartus archive? We need to check other IP settings as well.

Regards

[Ash_R_Intel]

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