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Receiving shifted 8 bit data with cyclone v custom phy transceiver ip.

Altera_Forum
Honored Contributor I
917 Views

Hi, 

 

I'm using cyclone v custom phy ip configured as single full duplex channel and 125mhz ref clk. 

 

Here I'm using only custom_phy ip and simulating its behavior using a test bench. I'm not using any reconfiguration controller and embedded controller to configure it. I just want to transfer 8/16/32 bit parallel data and receive the same using Self Loop back option. 

 

On transmitting 8 bit parallel data, I'm receiving 8 bit parallel data with 1 bit shifted arithmetically to right (i.e. sra) even i've disabled bit slip mode. And if i enable bit slip mode during ip configuration, I'm getting data shifted by 3 bits (sra). 

 

I didn't find any example design for custom_phy. If anyone come across this issue, plz share any doc and suggestion. 

 

thanks and regards
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1 Reply
Altera_Forum
Honored Contributor I
86 Views

You can find some example on alterawiki.com. The first example is for Custom PHY. That does't use manual mode but sync state machine mode, but it would be still helpful. 

http://www.alterawiki.com/wiki/cyclone_v_transceiver_phy_basic_design_examples 

 

If you don't use an encoder, such as 8B10B, it is difficult to find word boundary automatically (in manual/sync state machine mode) because there is no special bit stream which can be used as a word alignment pattern. In general, K28.5 code is used as a word alignment patter if 8B10B encoding is used.
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