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Hello!
Are there some techniques to reduce logic element usage when developing some projects with DSP builder?
I know something about folding without time-multiplexing, but just a little.
Do system clock frequency and sample rate correlate with logic element usage?
I'm building pretty simple module for my accelerometer, that implements atan function and is used to calculate angle using data from the sensor. And this project is using 6k logic elements! This is a lot, I think.
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DSPBuilder looks at sampling rate and system clock and works out folding accordingly so if the ratio is 2:1 (folding factor) it can design for shared resource. If your clock is 10times faster you can celebrate...
Additionally you can move logic or registers to ram blocks through settings in the synthesis token
