Reference Clock Input for High-Speed Transceivers in Terasic TR4 Eval Board

[Altera_Forum]

I am trying to use the Startix IV FPGA on the TR4 Eval Board from Terasic to receive a 15-bit word at 2.3Gbps. The channels use differential signalling and are source synchronous. Also, I have the transmitter clock available.  

 Since the data rate (2.3Gbps) is greater than that supported by the LVDS receivers on the TR4 board, I need to use the high-speed IO transceivers to receive the data. The TR4 board has 16 high-speed IO transceivers (routed to 2 HSMC connectors upto 6.5Gbps) which can be used for this purpose. Since the 15 channels are source synchronous, I would like to provide the reference clock as an input to the FPGA to be used by the transceivers. But, the reference clock inputs to the IO transceivers on the TR4 eval board are not routed out to the HSMC connectors. This makes it not possible to provide the source clock as the reference clock to the transceivers (REFCLOCK pins). My questions are:  1) Is it possible to provide the source reference clock to the IO transceivers through some other port (like the LVDS clock inputs)?   2) Can it be guaranteed that all the 15 received channels would exactly align in phase? Since the channels are source synchronous, the data received from all channels needs to be phase aligned to reconstruct the correct word.  3) Can I rely on the CDR function of the IO transceivers to recover the clock, without supplying any reference clock? If I do so, is there any guarantee that all 15 channels would be aligned in phase (see (2) above)?  Anybody sharing their experience or links to some literature would be highly appreciated.

[Altera_Forum]

--- Quote Start ---   1) Is it possible to provide the source reference clock to the IO transceivers through some other port (like the LVDS clock inputs)?    --- Quote End ---   You'll have to check the schematic. If you can access a CLKIN pin rather than a REFCLK pin, you can use a PLL to also provide the transceiver reference clock.    --- Quote Start ---   2) Can it be guaranteed that all the 15 received channels would exactly align in phase? Since the channels are source synchronous, the data received from all channels needs to be phase aligned to reconstruct the correct word.   --- Quote End ---   No. All the SERDES lane parallel output data will have the bits packed into words in sequence, but the start bit can vary between channels. You will need to use a pattern in the received data to align words. Can you control the data pattern?    --- Quote Start ---   3) Can I rely on the CDR function of the IO transceivers to recover the clock, without supplying any reference clock? If I do so, is there any guarantee that all 15 channels would be aligned in phase (see (2) above)?   --- Quote End ---   If your reference clock can be routed to the board, then use a PLL, and then use the PLL output as the REFCLK. If you cannot access a CLKIN pin, but there is a 100MHz reference clock on the board, use a PLL to create a reference clock with a matching lane rate and that should be sufficient to get the CDR to start in lock-to-reference mode, and then transition to lock-to-data mode.    --- Quote Start ---   Anybody sharing their experience or links to some literature would be highly appreciated.  --- Quote End ---    Read the transceiver docs at the top of this page  https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html  PS. I'm using the Stratix IV GX Development kits, so am familiar with the IP you need to use :)  Cheers, Dave

[Altera_Forum]

Hi knjayanth 

 I believe you can send through other ports but normally for transceiver you would have the CDR or the 3rd party device should come with CDR capabilities. Otherwise it would be very hard.  For the 15 channels, you might need to look into bonded mode. That would ensure the channels to channels are aligned.  This will depends on the device you are interfacing with. Normally it would still required a refclk. Of course in the case it does support CDR it could recovered the clock from the transmitted data.