Hi,I planning to develop a SATA interface to plug a SSD to save video sequences. I would like to use the cyclone IV GX family. I have found a development kit and a daughter card (cyclone IV GX development kit and SATA/SAS HSMC Card by Terasic) but I am still searching for a SATA IP. I have found 3 IP by nuvation / intelliprop / asics.ws but only intelliprop IP seems to be ready for Altera & cyclone IV GX. I was expecting a price around 5000$ but it's really more expensive (>x5). So I would like to know what solutions are used by other designer : other commercial IP ? difficulty of developing a SATA interface from scratch ?... Thanks for helping.
You can use SATA/SAS without additional chips according to http://www.altera.com/technology/high_speed/protocols/sata-sas/pro-sata-sas.htmlYou'll only need a small board to interface transceivers with a SATA connector.
Thanks for your advice. It could save a little money to do my own daughter card.But my main problem is more about the IP which cost 25,000$ (550 for the Terasic daughter card). Very expensive and low level only (needs a controller to manage data, file system...).
You can develop your own SATA IP. It is not as complicated as the core price leads to believe. Unfortunately, I cannot share the source at this point but here is what you will need:1- A good understanding of transceivers, especially reset sequences - read all the erratas. 2- SATA specs ($25) 3- ATA/ATAPI specs - most of it is free 4- Some kind of processor that will handle the commands (NIOS for example) One of the challenges we ran into was the lack of compliance by the devices out there. Most of them follow the specs, but in some instances they behave in ways that are not documented. A SATA analyzer comes in very handy here. Before we had access to a SATA analyzer, we just made the hardware impersonate a host and started sending commands to a hard drive and figured out the responses. Also, since you will be developing your own IP, you can tailor it to your needs and save on logic. If you develop your own card, make sure you have both host and device connectors - the connector is the same but the TX and RX pairs are reversed. Having both host and device will come in really handy during development. Expect the core to take about 160 hours of coding. If you are mimicking a file system or implementing a SCSI device, you will need to spend some more time - this is work you will have to do anyway. None of these tasks are complicated, but they will require some research and implementation time. When we did the analysis, the cost of developing vs buying was a wash so we opted to develop our own in order to gain the experience. The 25K price is in the lower end - some quotes we got were way above this. Good luck!
ironmoose, I've faced with the same problem with rx_signaldetect in Arria 2 GX 125 demo board as you not so far ago in another topic. I've also applied the ALTERA's suggestion but rx_signaldetect still stuck high. Could you please explain in more detail about this. How did you solved the problem with rx_signaldetect ?
This is the link I followed and rx_signaldetect started working. Make sure you modify your qsf file as indicated.http://www.altera.com/support/kdb/solutions/rd04042011_919.html?gsa_pos=1&wt.oss_r=1&wt.oss=rx_signa...
Yes, I've followed this link but can't understand the correct form of this assignmentI've tried this:
set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to "top_level_board:top_level_board|top_level_Device:top_level_Device|ALTGX1_alt4gxb:ALTGX1_alt4gxb|rx_datain" set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to "top_level_board:top_level_board|top_level_Host:top_level_Host|ALTGX2_alt4gxb:ALTGX2_alt4gxb|rx_datain"this
set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to "top_level_board:top_level_board|top_level_Device:top_level_Device|ALTGX1:ALTGX1|rx_datain" set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to "top_level_board:top_level_board|top_level_Host:top_level_Host|ALTGX2:ALTGX2|rx_datain"this:
set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to "top_level_Device:top_level_Device|ALTGX1:ALTGX1|ALTGX1_alt4gxb:ALTGX1_alt4gxb_component|rx_datain" set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to "top_level_Host:top_level_HOST|ALTGX2:ALTGX2|ALTGX2_alt4gxb:ALTGX2_alt4gxb_component|rx_datain"and this:
set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to "ALTGX1:ALTGX1|ALTGX1_alt4gxb:ALTGX1_alt4gxb_component|rx_datain" set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to "ALTGX2:ALTGX2|ALTGX2_alt4gxb:ALTGX2_alt4gxb_component|rx_datain"but nothing helped. How did you assigned ? P.S. I'm using Quartus 11.0 SP1 Here are my ALTGX.v in attachments
thanks for your advice ironmoose.I am waiting the answer for other quote but 25k$ seems to be a standard price. Not interesting at all : encrypted files, 1 fpga family... Do you have a SATA device simulation model ?
Tue,set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE ON -to rx_data_in  rx_data_in  is your signal from the top level entity. For example, the top level file has: module top_of_project (input clk, output led, input [1:0] rx_data_in) ... Do not put there signals from any descending hierarchy.
SebastienG,I do not have a model for that. Modeling a device is as much work as actually implementing it. Yes, another deterrent from the commercial solution was that the cost was per project. That did not make any sense to us. When we buy IP from Altera, they don't ask us how many projects we will be using the IP on. When/if you start on the project, I can answer your questions along the way.
We used a LeCroy STX-231 (I may be wrong about the 231 number). It is extremely easy to use any gives a lot of information about the packet content and decodes a number of protocols, including scsi. You can download samples from their site to see how it presents the data. The tool shows you crc errors, run length errors, timing errors...
Ironmoose,I know you said that you could not share the source code for your project. But, would it be possible to share the settings for the transceivers? I assume you used altgx blocks. I am about to go through the process of trying to figure out all the setting far the altgx mega-wizard. Thanks.
--- Quote Start --- Here you go. You will have to monkey around with the settings to turn the correct options on. Some options depend on settings on the following pages to be enabled. --- Quote End --- Thanks. This will be very helpful. I appreciate it.
Ironmoose,I’m trying to implement the SATA protocol using the Stratix 4 ALTGX transceiver. We have our own SATA controller. We are doing the 8b/10b encoding in the link layer as the SATA standards specifies. However in the “Transceiver Architecture in Stratix IV Devices” document it says: In Basic functional mode, you can enable the optional rx_signaldetect signal (used for protocols such as SATA and SAS) only if you select the 8B/10B block. This will not work for us. We need the rx_signaldetect signal, but we can’t do the 8b/10b in the PHY layer since we are already doing it in the link layer. how did you get around this problem. I did noticed that is easy to trick MW into providing the rx_signaldetect output without having to select 8b10b encoding, and it does seem to work in simulation, but will it work in real hardware? skg
Yes, I noticed that you cannot have one without the other. We used the 8B/10B block provided by the mega wizard and that worked fine. The ALTGX will give you the PHY layer and the 8B/10B. You will then need to add the scrambler and the rest on top of that to complete the link layer.Is there a reason you are not using the 8B/10B provided by the ALTGX config?
thanks ironmoose for your reply;The reason we cannot do 8b/10b in the PHY is because our SATA controller already does it in the link layer. we would have to bypass the 8b/10b in the link layer in order to use the one in the ALTGX. I am using the FPGA to emulate an ASIC and the PHY in the ASIC does not have 8b/10b encoding. An Altere FAE told me that another customer had tricked the MW to provide the rx_signaldetect without selecting 8b/10b and it worked for them. So, I am thinking of trying that myself. The way to trick MW is to select 8b/10b and then select the rx_signaldetect port and then unselect the 8b/10b and the rx_signaldetect port remains there. I tried it in simulation and it does do the right thing. I was able to do the COMRESET/COMINIT sequence. Another question I have is how did you do change the speed of the ALTGX? The appnote recommends two methods. 1) have 3 mif files one for gen1, gen2, gen3 and then use the altgx_reconfig block to change the config of the altgx. 2) use the rate_switch_cntrl to change the clock divider to 1, 2, or 4 to change the tx clock. I tried method 2 which is easier to implement and it worked in simulation. skg