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Altera_Forum
Honored Contributor I
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how to use external pll for altlvds_tx cyclone iv

i need to interface a lcd driver device with a FPGA throught LVDS port. the FPGA is cyclone iv EP4CE30F23, it used as lvds transmitter . the lcd driver device has lvds interface, it used as lvds receiver. In receiver, the lvds receiver timing diagram is showed in pic1 . For example , the FPGA transfer 7 data via one lvds channel , so the lvds channel number is 1, the deserializtion factor is 7. when the lvds out data rate is 70Mbps , the output clock rate is 10MHz. 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12799&stc=1  

my questions: 

[1] How can i use altlvds_tx ip core generate waves like pic1 ? 

[2] when i use internal pll for altlvds_tx , i find the range of phase alignment between tx_outclock and tx_out is from 0 to 51 degree, it can't meet the requirements of pic1. how can i resolve this question ? 

[3] when i use external pll for altlvds_tx , i find that it can adjust phase alignment between tx_outclock and tx_out , but i don't know how to calculate the phase . i use altpll ip core generate fast clock and slow clock , but how to calculate the phase of fast clock and slow clock ? when use external pll for altlvds_tx , it must use tx_syncclock , how to calculate the phase of it? 

 

Thank you for your help! 

 

Leo
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