SGDMA Polling Mode

[Altera_Forum]

Hi, 

 Can anyone shed more light on how the SGDMA works in Polling Mode ?  I have a qsys system with dedicated on chip memory to hold the descriptors (DESC_MEM_BASE). If I enable the polling mode in the SGDMA, will it iterate through all the descriptor locations in DESC_MEM_BASE until it finds one with OWNED_BY_HW bit set ? Or does it poll only on the first location in DESC_MEM_BASE, where SW needs to write the first descriptor in a link list ?  Much thanks in advance !

[Altera_Forum]

I've never used it before but basically it keeps polling a descriptor until it's hardware owned bit gets set. So the linked list doesn't get traversed but instead it's meant for easily starting the SGDMA back up. So normally the SGDMA hits the end of the chain (owned by hardware = 0), but with this polling bit enabled all you have to do is flip the owned by hardware bit on the descriptor the SGDMA is waiting on instead of starting the engine back up again. 

 This feature is really meant for high latency links like PCIe. So instead of you having the CPU starting the SGDMA back up by accessing the CSR across the PCIe link you let the SGDMA start itself back up by having it continously polling the owned by hardware bit. This assumes that descriptors are located in the host memory. Also make sure you set the timeout counter register accordingly otherwise you might kill your link performance with the SGDMA constantly reading the owned by hardware bit.

[Altera_Forum]

Thanks BadOmen. I'm preparing a couple of tests to understand this feature better. 

    --- Quote Start ---   This assumes that descriptors are located in the host memory.   --- Quote End ---   Any constraints in specifying the descriptor memory space?

[Altera_Forum]

By host memory I mean SDRAM connected to the host. It's common to have the SGDMA in the FPGA fetch descriptors and data from the host memory. I only mentioned this to put the polling mode into context since if you are using Nios II enabling polling doesn't really make sense since you have a low latency connection to the SGDMA CSR port using Nios II (so it's quick to get the SGDMA started back up again). 

 The constraints have more to do with PCIe and the host itself. For example you need to make sure when you pass pointers to the SGDMA that they are phyical memory locations and not virtual address since the SGDMA doesn't have access through the CPU MMU. With PCIe I think there are limitations on bursting across boundaries, I don't know the details about that one.   In general with the descriptors the only constraint is that they need to be placed on 32-byte boundaries in order for the SGDMA engine to fetch them correctly.