Most build SSRAM controllers using counters to time the off chip signals. That particular SSRAM supports bursting so the first step would be to check out the data sheet and figure out what type of off-chip timing will be need before designing anything. If you plan on also accessing the flash on that bus then you'll need to make your component a tri-state slave so that it can be shared behind a tristate bridge.
In the SOPC Builder handbook is a couple of chapters about building components. In particular you want to keep an eye out for the component editor documentation and perhaps the .tcl reference as well. Last but not least you'll need to become familiar with the Avalon specification since you'll be building a component with an Avalon slave port or Avalon tri-state slave port depending on which type you choose.
