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Sdram high preformance MegaCore

Altera_Forum
Honored Contributor II
‎02-07-2010 09:29 AM
1,081 Views

Hi all, 

I am trying to create three SDRAM Mega cores controllers that will work sepratly. After creating the MegaCores I discovered that there is usage of tree pll's in my design. Could I reduce the number of pll by deriving clock's outside the MegaCore (external pll).  

Thanks any way  

Elad
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Altera_Forum
Honored Contributor II
‎02-08-2010 06:57 AM
369 Views

The high performance cores require a PLL each. 

 

Jake
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