Stratix 10 Phylite IP , deviation in data sampling at different groups(Input Path Signal)

[NMR]

Hi ,

Configuration detail:

Problem Statement:

For group 0 data is sampled correctly as expected but for group 1 data to core signal the data sampled internally by phylite is shifted by 16bits(Starts sampling 2 clk earlier itself)

For checking if it's due to RTL interchanged group 0 and 1 but issue also got reversed, so not an issue from RTL rather internal sampling 

So tried increasing rd latency but it only shifts the rd valid signal not the internal sampling. 

Query:

Is there a method to control data sampling and address the deviation in data sampling between different groups, even though one group is a copy of the other?

Group 0

Group 1

[NMR]

Hi team,

I am looking forward for your reply

[Ash_R_Intel]

Hi,

I think there might be something to do with the read latency. Please follow the guidance on the following webpage:

6.3.1.1. Read Latency

Regards

[NMR]

Hi Ash_R,

Thanks for your consideration.

I checked this PHY Lite IP configuration settings with the example simulation design where I did not encounter this issue 

[NMR]

Hi Ash_R,

In dynamic reconfiguration , though I increase the tap value around mid(262) for pin input , I didn't find any delay in actual simulation .I referred the below one. Here I have doubt that how will we select the dq pin between 2 and 9.Additionally at specific pin selection (from 2 to 9) , what  I need to keep at field[8:7]?

Please help me with this

[Farabi]

Hello,

Bit [8:7] and bit [6:4] are used together to select DQ pins:

bit[8:4] = {2'h1, 3'h0} -> DQ0

bit[8:4] = {2'h1, 3'h1} -> DQ1

bit[8:4] = {2'h1, 3'h2} -> DQ2

bit[8:4] = {2'h1, 3'h3} -> DQ3

bit[8:4] = {2'h1, 3'h4} -> DQ4

bit[8:4] = {2'h1, 3'h5} -> DQ5

bit[8:4] = {2'h2, 3'h0} -> DQ6

bit[8:4] = {2'h2, 3'h1} -> DQ7

bit[8:4] = {2'h2, 3'h2} -> DQ8

bit[8:4] = {2'h2, 3'h3} -> DQ9

bit[8:4] = {2'h2, 3'h4} -> DQ10

bit[8:4] = {2'h2, 3'h5} -> DQ11

And about the abnormal behavior between groups, could you please run the simulation waveform showing the operation of all PHY Lite IP signals of both groups in one view.

So we can get the timing relationship of rdata_en, strobe_io, and rdata_valid of both groups in their testbench (and then check if there are any differences)

Could you please disable the dynamic reconfig in the IP and test again to see if the issue still happen?

regards,

Farabi

[NMR]

Hi Farabi,

Thanks for detailed explanation on dq pin selection.

Below is the simulation waveform on PHY Lite IP signals for both the group 0 and group 1

Group 0

Group 1

[Farabi]

Hello,

1. Disable dynamic reconfiguration in the IP and test again
2. Do not use the group copy feature (setup group 1 manually) and test again

regards,

Farabi