FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

Stratix V Transceiver Architecture

Honored Contributor II

Has anyone successfully implemented 4 independent 10G Low Latency PHY transceivers with 4 separate refclks? I know it can be done with two independent PHYs by assigning one on the left and the other other on the right. However, I need 4 PHYs. I have tried compiling with them as 4 separate single-lane PHYs and as 2 dual-lane transceivers with 2 TX PLLs and 2 Refclks. Both fail in the compile process with a "not properly connected" message. I am worried that this may not be architecturally possible. 


btw, this is using Quartus 12.1 with SP0 installed. 


Thanks in advance
0 Kudos
1 Reply
Honored Contributor II

Hi m13engr, 


In my case I need to implement 7 independent 10G Low Latency PHY transceivers. I got 3 independent channels and I couldn't connect any more, I also tried the two options that you mentioned. Did you find a solution?