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Stratix V Transceiver Architecture

Honored Contributor II

Has anyone successfully implemented 4 independent 10G Low Latency PHY transceivers with 4 separate refclks? I know it can be done with two independent PHYs by assigning one on the left and the other other on the right. However, I need 4 PHYs. I have tried compiling with them as 4 separate single-lane PHYs and as 2 dual-lane transceivers with 2 TX PLLs and 2 Refclks. Both fail in the compile process with a "not properly connected" message. I am worried that this may not be architecturally possible. 


btw, this is using Quartus 12.1 with SP0 installed. 


Thanks in advance
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Honored Contributor II

Hi m13engr, 


In my case I need to implement 7 independent 10G Low Latency PHY transceivers. I got 3 independent channels and I couldn't connect any more, I also tried the two options that you mentioned. Did you find a solution? 



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