FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5878 Discussions

TSE 1000MHz clock phase

Altera_Forum
Honored Contributor I
1,041 Views

Hi, 

 

I use ethernet port on terasic DE3 and DE2-115, GMII and RGMII respectively. The clocks are both 125MHz, could anyone tell me any requirement for the timing shift? It seems in RGMII mode I have to shift the clock signal by 90 degree.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
88 Views

not entirely true. if it is a marvel phy, there is a mdio register that causes the phy to perform the needed clock shifts. by default, rgmii requires tx data to be center aligned, and rx data will be edge aligned, necessitating a 90deg shift for the RX data. 

 

if you are using a more recent quartus, there is an example sw project for rgmii that sets this bit appropriately. 

 

--dalon
Altera_Forum
Honored Contributor I
88 Views

Thank you dalon now I understand this. So gmii does not have such a thing, right?

Reply