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Altera_Forum
Honored Contributor I
983 Views

TSE 1000MHz clock phase

Hi, 

 

I use ethernet port on terasic DE3 and DE2-115, GMII and RGMII respectively. The clocks are both 125MHz, could anyone tell me any requirement for the timing shift? It seems in RGMII mode I have to shift the clock signal by 90 degree.
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Altera_Forum
Honored Contributor I
30 Views

not entirely true. if it is a marvel phy, there is a mdio register that causes the phy to perform the needed clock shifts. by default, rgmii requires tx data to be center aligned, and rx data will be edge aligned, necessitating a 90deg shift for the RX data. 

 

if you are using a more recent quartus, there is an example sw project for rgmii that sets this bit appropriately. 

 

--dalon
Altera_Forum
Honored Contributor I
30 Views

Thank you dalon now I understand this. So gmii does not have such a thing, right?

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