FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

TSE without MDIO

Altera_Forum
Honored Contributor II
962 Views

Greetings, 

 

I have a board with several Vitesse phys, each one of then with 4 ports. All the phys are connected to my Arria II GX through a SMI bus. 

So far I've been able to configure the phys, on NIOS (this will be later done by hardware only), through a custom MDIO module connected to some PIOs. The phys are getting link with the link partner (my PC) and the registers says that the MAC side auto-negotiation is complete and link is up. All fine. 

But when I try to exercise it sending some packets with bittwist from my PC, I see no signal changes on TSE RX pins. 

 

So, I suppose TSE is not properly initialized, but how can it be done since it does not have MDIO to get information from the phys registers?  

 

Is there a way to manually configure\initialize the MAC without MDIO at TSE IP core? 

 

Thank you !!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
255 Views

 

--- Quote Start ---  

Is there a way to manually configure\initialize the MAC without MDIO at TSE IP core? 

--- Quote End ---  

 

 

MAC Configuration Register Space, chapter 5 of TSE User Guide. :oops: 

 

Thank you.
0 Kudos
Reply