FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6019 Discussions

Testing RX SERDES with a known value

Altera_Forum
Honored Contributor II
1,279 Views

I'm testing my system and I'd like to associate a known value to a RX Serdes Input. When instantiating it in top module I'd like to put my 8ch like .rx_in(8'hFF) but when I tried to do that I just receive this error below 

 

Error (15871): Input port DATAIN of DDIO_IN primitive "SERDES:serdes|altlvds_rx:ALTLVDS_RX_component|SERDES_lvds_rx:auto_generated|SERDES_ddio_in:ddio_in|ddio_ina_1" must come from an I/O IBUF or DELAY_CHAIN primitive 

 

I tried to create a reg and the associate a reg to rx_in but again without success. 

 

Thanks 

Danilo
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
201 Views

if you are simulting then use testbench to instantiate your design and feed input through io

Reply