FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6591 Discussions

The data receiving using GPIO

ZC0001
Beginner
‎01-07-2020 06:23 AM
592 Views

Hi,all.

I plan to use Cyclone 10gx GPIO IP in my project for ADC data receiving. I want to know if this IP can support 200MHz clk rate with DDIO mode for LVDS data. Looking forward your reply. Thanks.

0 Kudos

Link Copied

1 Reply
Rahul_S_Intel1
Employee
‎03-10-2020 09:46 AM
479 Views

Hi ,

Intel psg is not supporting the maximum date rate of maximum clock frequency in which LVDS can operate , i am kindly requesting to do the simulation to know the data results

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.