FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

The problem about setting up the FIFO's deep

Altera_Forum
Honored Contributor II
1,296 Views

Hi guys, 

I have a big problem when I use the DCFIFO mega function. I need to store large amounts of data to achieve the data delay function. When I use the small FIFO(deep 1024),it works well. However when I increase the deeps of FIFO, it goes bad(deep 32768).(Writing and reading are not the same ) What happened ? I am confused! Is there anyone who meets the similar prolem? I'm looking forward to your suggestions! Sincere thanks!
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
577 Views

Ive had deep fifos, and never had a problem. You will need to post more details. 

 

Have you changed any other settings, like the lookahead mode?
0 Kudos
Altera_Forum
Honored Contributor II
577 Views

Thank you for your reply! 

yes, I turn on the show-ahead mode and my FIFO wide is 14bits. Did you set up any Timing Constraints for the FIFO when it gets big?
0 Kudos
Altera_Forum
Honored Contributor II
577 Views

not specifically, just make sure you have constraints on both clock domains.

0 Kudos
Altera_Forum
Honored Contributor II
577 Views

Can you explain it in detail? I am a novice....:oops:

0 Kudos
Altera_Forum
Honored Contributor II
577 Views

I have same problem.  

I use 32bit input and 8bit output FIFO, the fifo deep cannot exceed 1024 words (32768 bits).
0 Kudos
Reply