Triple Speed Ethernet

[Altera_Forum]

Hi all,  

 I am working on a project where we need to send data from FPGA to computer via ethernet. We are using triple speed ethernet IP core and I couldn't find out how the core does the addressing. In user guide it says that on Mac transmit operation I think the core sends the preamble, sfd, the destination address, source addresses, the data, the padding and crc. Does the ip core sends all of them automatically? I found out that the source address can be configured by setting the mac registers, but I don't know where can I set the destination address.  Since I am only trying to send data from fpga to computer, which mac registers are critical? Can someone tell me which registers do I need to configure?   Thanks.

[Altera_Forum]

Only the preamble and sfd are sent automatically by the TSE core. The rest of the Ethernet packet, including the header, must be part of the packet sent on the Avalon Stream interface. 

For the registers there isn't a lot to configure. There is at least the interface speed, and the MAC address that is used for the MAC filter on the receive interface (or you can also set the promiscuous mode, of course).

[Altera_Forum]

Thanks for your answer, that helped a lot:)  

I also have a question about the testbench that TSE core provides. I simulated the testbench in modelsim and try to understand which registers are configured and how they are configured. But the register addresses in the megafunction user guide and the addresses in the test bench are very different. I couldn't give a meaning to the register configuration there. Is there a problem with the test bench or the user guide?

[Altera_Forum]

I don't know about the test bench, but until now the information I read in the user guide was correct. 

You must be careful about one thing: the Avalon Memory Mapped interface uses native addressing, which means that the address bus selects an address in the 32-bit space. On the other hand the documentation describes the interface seen from the software side on a CPU that uses an 8-bit addressing. As a result you must shift the address seen in the documentation by two bits to get the real value you need to put on the address bus. As an example to access the TX Command Status Register, documented as address 0x0E8, you need to put 0x3A on the address bus. The differences you see could come from there.