Triple speed ethernet ip on cyclon v resource allocation

[yairShapira]

Hi All.

I have built an 8 port ethernet mac with sgmii pcs and embedded pma using the triple speed ethernet ip from the  quartus 18.0 IP Catalog. I am using cyclon V gx.

after connecting everything, I have received the following errors during fitting :

Error (175020): The Fitter cannot place logic Channel PLL that is part of Triple-Speed Ethernet Intel FPGA IP julian_eth1 in region (0, 40) to (0, 42), to which it is constrained, because there are no valid locations in the region for logic of this type.

Error (11997): Design has 10 tx channels, 10 rx channels, exceeds the capacity of targeted device, 9 channels.

Error (11999): Channel(s) under reference clocks: mac_ref_clk are 10 tx channels, 10 rx channels, which exceeds the capacity for the targeted device's HSSI strip, 9 channels.

Can anybody think of a cause for this errors ? I have implemented 8 ports only. why does the quartus try to implement 10 ?

Thanks in advance

yair.

[Deshi_Intel]

Hi Yair,

Is your TSE IP design using CMU PLL ?

If yes, then I suspect certain transceiver RX channel is being converted to become CMU PLL to clock TSE IP. This could explained why total consumption is more than 8 channels.

You can reduced your design TSE IP count to lower channel like maybe 4 channel, get a passing fitter compilation, then study the fitter report to see how many CMU PLL is being consumed

Thanks.

Regards,

dlim

[yairShapira]

Hi.

Thanks for your reply.

Yes , it is a CMU PLL. For Cyclon V , The TSE uses only CMU PLL. However , I was thinking that the CMU PLL Is a part of each GBX transceiver. So why should he dedicate a transceiver to be used as a PLL...

Any way instead of using an 8 port block, I am trying to use single port blocks, and grow gradually until I reach the 7 ports I need. for now I fitted 2 successfully. and currently the usage is :

2/9 Standard RX PCSs

2/9 PMA RX Deserializers

2/9 Standard TX PCSs

2/9 PMA TX Deserializers

3/9 Channel Pll's

Thanks for all your help

Yair.

[Deshi_Intel]

Hi Yair,

The reason behind is there is no standalone CMU PLL design block.

It's basically a dual function shared design block where user can choose to either use it as

• CDR design block of Rx channel
• or as CMU PLL

So if user choose to use as CMU PLL, that RX channel can't be used anymore

Else if user choose to use it as Rx channel then there is no more CMU PLL

Thanks.

Regards,

dlim

[yairShapira]

Hi.

So I finally managed to fit 7 channels. and found that it is possible only when I leave channel 1 and 4 free. So the Quartus uses channel 1 and 4 as CMU.

Unfortunately this dose not feet my already made PCB, So I will have to make another layout.  I have 2 questions :

1. Do I have to use the CMU ? I have seen in the handbook that there is an option to use FPLL, but there is no flexibility in the TSE Wizard.

2. If I must use channel 1 and 4 as CMU, Then how should I connect them in the PCB ? leave them open ?

Thanks for all your help Dlim , really appreciate it.

Regards

Yair

[Deshi_Intel]

Hi Yair,

It's good design practice to always test out design in Quartus fitter compilation first before proceed with board design.

Only channel 1 and channel 4 have "centralize clock network" to spam the clock network to clock all 6 channels within one transceiver bank.

• You can read more about Cyclone V transceiver clocking in chapter 2 of below user guide doc
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf

Now to your questions.

1. Do I have to use the CMU ? I have seen in the handbook that there is an option to use FPLL, but there is no flexibility in the TSE Wizard.

• I am not quite sure where you see it but anyway the doc most of the time don't explicitly speel out the supported feature is for which FPGA product family.
• Same IP may exist across different FPGA product family but the IP feature support maybe different due to changes of FPGA architecture
• To be safe, always launch the specific IP in your desired FPGA device (Cyclone V in your case) then check what's available support option. As you can see that only CMU PLL option is available in Cyclone V TSE IP

2. If I must use channel 1 and 4 as CMU, Then how should I connect them in the PCB ? leave them open ?

• You can always refer to FPGA pin connection guideline to check out how to connect FPGA pins on board
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf
• Page 21 mentioned unused GXB_Tx pin can be left float while unused GXB_RX pin can connect to GND
• I advise you to add series zero ohm resistor before short channel1/4 RX pin to GND. Then you will have the flexibility to either short it to GND or remove resistor to left the pin float

Thanks.

Regards,

dlim

[yairShapira]

Many Thanks Dlim.

Yes, as a beginner in FPGA complex IP's, sometimes I learn things the hard way :-).

I Thought that I have the FPLL Option to clock the transmitter, because I saw it in the Cyclone V transceiver handbook (device handbook volume 2):

"Transmitter PLL
In Cyclone V GX/GT/SX/ST devices, there are two transmitter PLL sources: CMU PLL (channel PLL) and
fPLL. The channel PLL can be used as CMU PLL to clock the transceivers or as clock data recovery (CDR)
PLL" (page 1-21).

So, I thought , if the TSE doesn't support it, may be I could use a different IP.

Thanks again

regards

Yair.

[Deshi_Intel]

Hey,

No worry. FPGA design indeed is complex and not easy to master.

So, just wonder is the TSE fitter issue resolved now once you switch to bigger FPGA device or you cut down on TSE channel usage ?

Thanks.

Regards,

dlim

[yairShapira]

Hi.

As I need only 7 channels for this project, I skipped ports 1 and 4, so they can be used as CMU, and now it fits o.k. I am trying to get everything to work and then I will re-design my circuit.

I am still wondering if there is a way to use the FPLL  instead of the CMU (as is seems like valid option in the Cyclone v transceiver hand book) maybe with a different IP ?

Thanks

Regards

Yair.

[Deshi_Intel · Accepted solution]

Hi Yair,

Yup, for CV TSE IP, CMU PLL is the only supported option right now.

Ya, sure, feel free to explore other IP as well. It may comes with different PLL support structure.

I believed the enquiry on TSE IP is addressed. Feel free to post new forum thread if you have questions on other Intel IP solution.

For now, I am setting this case to closure as Intel support structure is on a case by case basic.

Thanks for your understanding

Regards,

dlim