Unable to communicate through SPI slave to Avalon Master IP

[Altera_Forum]

Hello, I'm using Altera's SPI slave to Avalon Master Bridge IP to interface with a SPI master on a BeagleBone Black. Both sides are working with 3.3V CMOS logic levels. I'm using Qsys to connect the IP with the FPGA Avalon MM (please see attached qsys file) and exporting the SPI slave bus to the top level of the FPGA and routing the signals to pins connected to the BBB SPI master. On the BBB side I'm using the source code provided by Altera to interface with the IP Core using an external processor and replaced alt_avalon_spi_command with a SPIdev function (please see attached source code). 

  So far I've been able to probe the MOSI pin when writing a 0x00000001 to address 0x3c (this address is mapped to an LED on my SoC board and I have tested it's working before using Altera's LW Axi Master), here's the pattern:   0x7A 0x7C 0x00 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x3C 0x00 0x00 0x00 0x7B 0x01 SOP CH ID Trans type Size Address Data & EOP before last data byte   Which is consistent with the protocol on Altera's software library, but I haven't been able to read or write to any Address on the FPGA MM. I do get some activity on the MISO pin (below in hex), but it doesn't match with the protocol:   20 48 94 94 94 94 94 94 94 94 89 49 49 49 49 29 00 00 00 00 00 00 00 00   I verified that the SPI signals from the BBB are received on the FPGA SPI pins by putting then in output pins and probe them, the pattern is working fine, the CS signal is being asserted (active low), SCLK and MOSI are received properly.

[Altera_Forum]

Finally I got the IP to work, turns out I was using NSS pin as bidirectional, I don't get why that wasn't enabling the proper functioning of the core, the SCLK pin is still configured as bidirectional. Can someone shed some light on this matter? Thanks in advance!