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Using Altera PLL make 500Khz or below

jjang
Beginner
1,255 Views

When i Using ALTPLL, i Usually make 500khz and below xx kHz Frequency Clock. @ 50Mhz  / 100Mhz Input clock.

 

But Cyclone 5,  Different PLL IP Core. 

 - ALTPLL → Altera PLL,  so it doesn't support for Low Frequency Clock.

 does have any way to make 500kHz or 10kHz frequency Clock? 

 

 

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FvM
Honored Contributor II
1,201 Views

Hi,
just read PLL Intel FPGA IP messages thoroughly. It instructs you to enable physical output clock pararameters to configure cascaded output counters.

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FvM
Honored Contributor II
1,229 Views
Hi,
all Intel FPGA starting with Cyclone III have a post-scale counter cascading feature and can generate output frequencies down to a few kHz, also Cyclone V.

Regards,
Frank
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jjang
Beginner
1,214 Views

As Clocking and PLL User Guide.. 

 

Using PLL Clock (C1, C2. C3.C4), then that can though Global clock.

 

but to make a Clock as  a Logic (such as Counter).. will not connect to Global clock . .isn't it?

Global_Clock.PNG

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FvM
Honored Contributor II
1,202 Views

Hi,
just read PLL Intel FPGA IP messages thoroughly. It instructs you to enable physical output clock pararameters to configure cascaded output counters.

AqidAyman_Intel
Employee
1,138 Views

Hi,


I wish to follow up on this issue. Have you able to use the cascading feature to generate the low frequencies output clock?


Regards,

Aqid


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