We are having issue getting data out of the CIC core during simulation.

[PGigl]

We have built up a QSYS design with our own core feeding into a CIC core, feeding into a FIR core.  In our simulation we can see signals and data going into the core, and see the appropriate handshake signals coming out of the core's streaming interface, but the data shows up as unknown!​ Since it is built with IP, we cannot dive into the core to see where things have gone wrong.

[CheePin_C_Intel]

Hi Paul, As I understand it, you are observing some problem when simulating with the CIC IP. To ensure we are on the same page, just would like to check with you on the following: 1. What is the device that you are using? 2. What is the Quartus version that you are using? 3. Would you mind to further elaborate on the unknown output that you are referring to in the initial description? Some screenshots will be helpful for further understanding. 4. Mind share with me the CIC IP configuration ie .ip file will be helpful. 5. Just wonder if you have had any chance to try simulating the example design generated by the IP to see if the simulation is able to run? Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[PGigl]

1. What is the device that you are using? 5CSX

2. What is the Quartus version that you are using? 18.1 Standard.

3. Would you mind to further elaborate on the unknown output that you are referring to in the initial description? Some screenshots will be helpful for further understanding.

4. Mind share with me the CIC IP configuration ie .ip file will be helpful.

5. Just wonder if you have had any chance to try simulating the example design generated by the IP to see if the simulation is able to run?  ONe of the things on the to do list

[CheePin_C_Intel]

Hi Paul, Thanks for your update. Please feel free to update me on my previous inquiries 3 to 5. For your information, I have tested generating an example design with CV with CIC default settings. I am able to run the Modelsim simulation without issue. Thank you

[PGigl]

Regarding #5, how did you get the example to simulate. The example design did not include a Do file.  I ran the TCL script it had created, but was unsure as to the next step.  It would be nice if there was a readme file or other instructions, or did I just miss something. 

Here is a screen shot of the waveforms.

[CheePin_C_Intel]

Hi, Can you please try the following to see if you are able to get the simulation running after sourcing the TCL script: 1. Type “ld” to start compilation and elaboration 2. Select and add the signals that you would like to monitor to waveform 3. Then type “run -all” to start the simulation Thank you,. Best regards, Chee Pin

[PGigl]

​Thanks, the example simulates fine..

[CheePin_C_Intel]

Hi, Can you please try the following to see if you are able to get the simulation running after sourcing the TCL script: 1. Type “ld” to start compilation and elaboration 2. Select and add the signals that you would like to monitor to waveform 3. Then type “run -all” to start the simulation Thank you,. Best regards, Chee Pin

[CheePin_C_Intel]

Glad to hear that the simulation is working fine. You may refer to the example and start customizing from there. You may also refer to it and see if there is any discrepancy with yours and fix from there.

[CheePin_C_Intel]

Hi Paul, I will set this case to close for now. Please feel free to open a new case and referred to this case if you have any new inquiry related to the simulation. thank you.

[PGigl]

​Do not close the case! The example design simulates, but the real design does not! We noticed that the example design throughs error codes!  We went into the example codes BFM and set the "Forward pressure" variable to False, which disabled the "random" functionality, and caused the SOP and EOF inputs to behave normally, and eliminated the error - IN THE EXAMPLE DESIGN.  But we still are not getting data out of the real design, though our SOP and EOF match the example (once random was turned off in the example).

[CheePin_C_Intel]

Hi Paul, Thanks for your update. Would you mind to further elaborate on the example design error codes that you are referring to in your previous note? Regarding your design which seems not having CIC data output in simulation, would you mind to help to share with me a simple test design with a CIC IP which could replicate your current issue observation together with some screenshots so that I could have better understanding on the observation. Please feel free to share with me the detailed steps to replicate the observation in Modelsim simulation. I would like to perform replication on my side and further look into it to see if can spot any anomaly. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[PGigl]

Regarding the errors, they are error codes put out by the core, due to SOP and EOP relationship cased by the  FORWARD_PRESSURE defined as "TRUE"

We changed the FORWARD_PRESSURE definition to "FALSE" and the example simulation worked better.

Here is the code from the cicii_example_design_test_program.sv  that causes the randomness of the SOP and EOP signals.

 fork

    begin

      while(1) begin

        read_input_data_files();

        if(`FORWARD_PRESSURE=="TRUE")

         begin

          src_transaction.idles = ($unsigned($random()) % 10);

         end else begin

          src_transaction.idles = 0;

        end

        src_transaction.send_data();

        if(source_finished == 0) begin

          @(`SRC.signal_min_transaction_queue_size);

        end

      end

   end // source_data_thread

After comparing the two simulations, we noticed differences in the clock rates (ratio between clock frequency and sample rate). After playing with the clock frequency we are now starting to get data out, but only on one channel's time slot.

Can you provide any guidance and/or documentation on setting the clock and sample rates.

[PGigl]

Attached is the project with original clocking.  Under the simulation directory under C:\Intel_projects\micromeritics\CIC_design\m_293_20091_00_top there is a file mentor.do that will run  the simulation.  You will need to modify the directory locations in the scripts to match your location, else unzip to something like C:\Intel_projects\micromeritics\CIC_design

[CheePin_C_Intel]

Hi, Thanks for your update and sharing. Please allow me some time to look into them to see if can spot any anomaly. I will provide you an update on the progress by end of the week or as soon as there is any valid finding. Please ping me if you do not hear from me. Thank you.

[PGigl]

Here is the latest waveform that shows data only coming out on channel 7

​Some other oddities.  Jon has tried to generate test bench for his QSYS design and it fails to generate the TB.  I have the same design (older version) and I can generate the test bench without issue.  Can you try this on the design that you have.

.

[PGigl]

​The other thing we are looking at is how the BFMs are being called in the example versus the real design.

[CheePin_C_Intel]

Hi, Sorry for the delay. Thanks for the update and sharing of the screenshot. Just to update you on the progress on my side, I have replicated your observation of no valid output at CIC following you steps and shared ZIP. It seems like it is a complete design and I have tried to look into if can spot any anomaly. For your information, I have not yet been able to spot any specific anomaly yet. Currently, I am trying to mimic your CIC IP configuration and generate an example design to cross check if example design with your configuration is able to output data. I will have further discussion with peers specific on your finding where changing the frequency seems to enable output at CH7. Will keep you posted on the progress. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[CheePin_C_Intel]

Hi, Regarding your latest note on the generate test bench for the QSYS file, I believe you are referring to m_293_20091_00_top.qsys. I have tested test bench generation using Q17.0Std (due to no Q18.1Std installed in my local PC) and there is no issue with generation. Will further try out with Q18.1Std when I have access to server later. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[CheePin_C_Intel]

Hi, Just to update you on the latest finding. For your information, I have managed to perform simulation with IP (mimic your configuration) generated example design and there is no issue with the simulation after applying the fix that you mentioned in the previous note for test_program.sv. Input data and output data looks normal in the example simulation. As I further look into your design simulation and cross check with the example simulation, I observe that in your design, the first batch of in_data to CIC IP has invalid bit[17] = StX as shown in the invalid first batch of input data.png. I suspect that due to this invalid first batch of data, it leads to corrupted data for the subsequent output. I have then tested forcing the in_data to a dummy data in your top level file and rerun the simulation. After feeding valid data, I am able to see valid output at the CIC IP in the simulation as shown in the after_fix_first_batch_data_ok.png. It would be great if you could help to look into your data source to the CIC in_data to see what might have cause the first batch of source data to be invalid. Note that I am unable upload the screenshot to the case, probably due to server issue. Thus, I am sending them to you through email. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

[JAnde37]

Yes! The initial batch corrupted data coming out of reset was enough to hang the CIC. One simple fix and our design is simulating perfectly. Thank you!