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What detail is for a hardware-based divider in APLEX?

Altera_Forum
Honored Contributor II
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Hi, 

 

I read a DSP paper. It mentioned: 

 

The hardware-based divider supplied by Altera, configured as 16 bit by 26 bit, consumes 1123 LEs when it is synthesized for the same APEX device? 

 

I would like to implement it in new FPGA, such as Cyclone. How can I do it? Is there a magacore for that? 

 

Thanks,
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Altera_Forum
Honored Contributor II
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try ALTFP_DIV maybe (megawizard)

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