FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6445 Discussions

What detail is for a hardware-based divider in APLEX?

Altera_Forum
Honored Contributor II
‎02-17-2014 07:07 PM
900 Views

Hi, 

 

I read a DSP paper. It mentioned: 

 

The hardware-based divider supplied by Altera, configured as 16 bit by 26 bit, consumes 1123 LEs when it is synthesized for the same APEX device? 

 

I would like to implement it in new FPGA, such as Cyclone. How can I do it? Is there a magacore for that? 

 

Thanks,
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎02-17-2014 07:20 PM
203 Views

try ALTFP_DIV maybe (megawizard)

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.