FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5952 Discussions

What detail is for a hardware-based divider in APLEX?

Altera_Forum
Honored Contributor II
761 Views

Hi, 

 

I read a DSP paper. It mentioned: 

 

The hardware-based divider supplied by Altera, configured as 16 bit by 26 bit, consumes 1123 LEs when it is synthesized for the same APEX device? 

 

I would like to implement it in new FPGA, such as Cyclone. How can I do it? Is there a magacore for that? 

 

Thanks,
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
64 Views

try ALTFP_DIV maybe (megawizard)

Reply