What is Altera library for 16 bit Shift Register LUT with Clock Enable

[Altera_Forum]

I want to change from Xilinx desing code to Altera. 

But, I don't know what is altera library for following two xilinx library. If you konw it, let me know.   1) 16 Bit Shift Register Look-Up-Table(LUT) with clock Enable (http://toolbox.xilinx.com/docsan/data/alliance/lib/lib10_10.htm) 2) 2 to 1 Multiplexer for Carry Logic with General Output (http://toolbox.xilinx.com/docsan/data/alliance/lib/lib7_33.htm)   Thanks

[Altera_Forum]

For the first one, there isn't an exact replacement, you may design a wrapper to port existing code, if necessary. The second one is a very basic element that wouldn'n be instantiated directly to my opinion. But you possibly can find a replacement in primitives library. 

 I noticed, that Xilinx mentioned inference recommended with both components, in other words, they assume that you let the HDL compiler choose a suitable library component. In this case, you don't have to worry much how to port the code to another FPGA family.

[Altera_Forum]

I strongly agree with FvM. These components can all be inferred, and the coding is much easier and more understandable. Fot the sift register, there is a megafunction call altshift_taps that makes shift registers out of memories. I don't recommend instantiating that either, but letting Quartus infer them. If you go to Assignments -> Settings -> Analysis & Synthesis -> More Settings -> Auto Shift Register Replacement, which is set to Auto. On some X designs I've converted where the user instantiated this, I put in an RTL model, let Quartus figure it out, and ended up using less logic because of it(but a little extra memory.) Here's a model that should help: 

module SRL16E(Q, A0, A1, A2, A3, CLK, D, CE) ;  input A0, A1, A2, A3, CLK, D, CE; output Q;  reg [15:0] shift_reg; reg Q;  always@(posedge CLK)  begin  if (CE)  shift_reg <= {shift_reg[14:0],D};  end  always @ (A3 or A2 or A1 or A0 or shift_reg) begin  case ({A3, A2, A1, A0})  1 : Q = shift_reg[1];   2 : Q = shift_reg[2];   3 : Q = shift_reg[3];   4 : Q = shift_reg[4];   5 : Q = shift_reg[5];   6 : Q = shift_reg[6];   7 : Q = shift_reg[7];   8 : Q = shift_reg[8];   9 : Q = shift_reg[9];   10 : Q = shift_reg[10];   11 : Q = shift_reg[11];   12 : Q = shift_reg[12];   13 : Q = shift_reg[13];   14 : Q = shift_reg[14];   15 : Q = shift_reg[15];   default : Q = shift_reg[0];  endcase  end endmodule