Why PCIe signals tx_st and rx_st are different for CIV and CV in QSys?

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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Why PCIe signals tx_st and rx_st are different for CIV and CV in QSys?

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Why does "Cyclone V Hard IP for PCI Express" have tx_st and rx_st as Avalon-ST sink and Avalon-ST source in QSys, but "IP Compiler for PCI Express" for Cyclone IV have it only as Conduits?

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