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I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two output is x in the simulation. I just used the auto-generated pll simulation test bench. My quartus software is 16.1, and the device is cyclone V 5CEFA4.
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Hi,
Could you please refer the below reference design for Dynamic phase shift with Intel PLL IP core
Please let me know, how it works to you.
Regards,
Vicky
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What timeunit are you simulating with? PLL simulations can be really tricky about wanting a very fine grained simulation so I'd recommend trying with timeunit 1fs/1fs; and see if you get any different results.
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Hi,
Please follow the steps as mentioned in below application notes,
https://www.intel.com/content/www/us/en/programmable/documentation/mcn1424769382940.html#mcn1424940703121
please let me know, how it works for you.
Regards,
Vicky
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Hi Liu Jianjun,
Glad you resolved it.
Thanks,
Vicky
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