I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two output is x in the simulation. I just used the auto-generated pll simulation test bench. My quartus software is 16.1, and the device is cyclone V 5CEFA4.
Could you please refer the below reference design for Dynamic phase shift with Intel PLL IP core
Please let me know, how it works to you.
What timeunit are you simulating with? PLL simulations can be really tricky about wanting a very fine grained simulation so I'd recommend trying with timeunit 1fs/1fs; and see if you get any different results.
Please follow the steps as mentioned in below application notes,
please let me know, how it works for you.