altera_avalon_new_sdram_controller

[dicas3d]

I have a project with Dev board max1000 and altera_avalon_new_sdram_controller and in the last version of quartus prime lite give an error that I can't found this module in Qsys. Today I'm writing to you via mobile so I can't make to you a screenshot to show what connections we need to do but since this is a github project, I can show you the link that is https://github.com/dimag0g/nios_duino/blob/476950fa22f31b23a70c71ec2137ad0d9a84ab21/contrib/max1000/NIOSDuino.qar
. If anyone can say me how to easily replace this IP I will thanks.

[AdzimZM_Intel]

Hello!

For your information, the SDRAM Controller IP is already End Of Life.

If you want to use the IP, you might consider to use older Quartus version such 18.1 and earlier.

Besides, this design was created in Quartus Prime version 17.0.

For better functionality, you need to run it in Quartus version 17.0 as well.

Regards,

Adzim

[dicas3d]

Info (125068): Revision "NIOSDuino" was previously opened in Quartus Prime software version 18.1.0 Lite Edition. Created Quartus Prime Default Settings File C:/Users/Utilizador/Downloads/nios_duino-master/nios_duino-master/contrib/max1000/NIOSDuino_restored/NIOSDuino_assignment_defaults.qdf, which contains the default assignment setting information from Quartus Prime software version 18.1.0 Lite Edition.

And in the link here is the screenshot of qsys

[dicas3d]

I replaced altera_avalon_new_sdram_controller by altera_avalon_onchip_memory2 which has the same pinout. Is this IP Core replacement good (by good, I mean it gives exactly the same result)?

[sstrell]

It depends on if the design would work the same whether you are using external memory or onchip memory, since you are making that kind of switch.

[dicas3d]

Design uses external ram.

[sstrell]

Well, if you switch the component, you won't be accessing external memory anymore.

[dicas3d · Accepted solution]

I picked an Verilog Model from manufacturer. This is the only thing that is provided as IP Core from him. This is a file .vp and .v for 

NC-Verilog 

 And I don't know how use as an Qsys component. The main file is the .vp.