FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

altera soft lvds for max 10

Altera_Forum
Honored Contributor II
1,365 Views

Hi, i'm going to use lvds pairs on max 10m80e board. 

There is Altera Soft Lvds IP in Q14.1 

Can i use the ip core for transmitting data throught lvds pairs? 

I use camera link base protocol (7 is ser factor). 

Speed i need is about 20Mbps. 

How i can simulate the ip core? Just like an any ip core? I've tried but the core doesnt response
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
463 Views

There should not be any issues with that. 

 

Perhaps you might want to put more description to your failure symptoms.
0 Kudos
Altera_Forum
Honored Contributor II
463 Views

Wouldnt 20Mbps would be a little too low for J = 7. 

If not mistaken the minimum you would need 70Mbps for J =7.
0 Kudos
Altera_Forum
Honored Contributor II
463 Views

If the supported minimum data rate is higher than your requirement, you may try to look into performing oversampling at your receiver side to step down the data rate.

0 Kudos
Altera_Forum
Honored Contributor II
463 Views

I've created project. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=10918  

I'm using external pll, counter and altera soft lvds. 

serialization factor is 4. So the core should take 4 data bits from counter and serialize to 1 bit. 

I'm checking by signalTab. 

The core doesn't work.  

I took pll settings from max 10 lvds UG. (400 for inclock and 80 MHz for syncclock) 

 

What could be wrong?
0 Kudos
Altera_Forum
Honored Contributor II
463 Views

Fabian the transmitter model doesn't work at all. 

I tryed most simple model with internal PLL. I can see that the internal PLL is locked but nothig comes out. 

The receiver works fine. 

 

 

César
0 Kudos
Altera_Forum
Honored Contributor II
463 Views

Hi Fabian, 

 

Probably you could try simulating your design in Modelsim to see if similar issue observed?
0 Kudos
Reply