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Hi, i'm going to use lvds pairs on max 10m80e board.
There is Altera Soft Lvds IP in Q14.1 Can i use the ip core for transmitting data throught lvds pairs? I use camera link base protocol (7 is ser factor). Speed i need is about 20Mbps. How i can simulate the ip core? Just like an any ip core? I've tried but the core doesnt responseLink Copied
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There should not be any issues with that.
Perhaps you might want to put more description to your failure symptoms.- Mark as New
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Wouldnt 20Mbps would be a little too low for J = 7.
If not mistaken the minimum you would need 70Mbps for J =7.- Mark as New
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If the supported minimum data rate is higher than your requirement, you may try to look into performing oversampling at your receiver side to step down the data rate.
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I've created project.
https://www.alteraforum.com/forum/attachment.php?attachmentid=10918 I'm using external pll, counter and altera soft lvds. serialization factor is 4. So the core should take 4 data bits from counter and serialize to 1 bit. I'm checking by signalTab. The core doesn't work. I took pll settings from max 10 lvds UG. (400 for inclock and 80 MHz for syncclock) What could be wrong?- Mark as New
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Fabian the transmitter model doesn't work at all.
I tryed most simple model with internal PLL. I can see that the internal PLL is locked but nothig comes out. The receiver works fine. César- Mark as New
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Hi Fabian,
Probably you could try simulating your design in Modelsim to see if similar issue observed?
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