Hi,
I want to use the altremote IP (Altera remote update) on a cyclone IV E system. An FPGA attached SPI flash contains a factory and an application
image (addresses 0 and 0x80000).
The factory image boots fine. The design uses a qsys component that has several IPs on the avalon bus. One of these is the altremote IP.
I can read/write all IPs just fine except the altremote core. I would expect that I can readback the bootaddress from address offset 0x10
after writing 0x80000 to this reg. But I only get back 0 on every register.
The altremote IP is configure with "Add support for writing configuration parameters" and "Add support for Avalon Interface".
What is the problem? Why is read/write to the bootaddress reg not possible?
The IP userguide mentions fmax=20Mhz for Cyclone IV. What's this fmax? Avalon clock in my case?
All IP register addresses are 32bit aligned, except the RECONFIG register (0x1d). Is this by intention? So I nee to do a byte access
to this unaligned address?
Quartus version is 16.1.
Regards,
Matthias
