FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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byte enables output of PICe

Honored Contributor II



I found in Altera's PCIE core that they use a separate byte enable signal for rx side avalon. This signal is not present in Xilinx's PCIE core. In Altera's PCIE user-guide, I didn't found anything about the validity of byte enable for "completion" TLPs. Only thing mentioned is that these byte enable signals are same as we found in Memory read/write TLPs. But since completion TLPs dont contain any byte enable signals can we safely use that byte enable signal to decode data from completion TLP?? 


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