FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5882 Discussions

byte enables output of PICe

Altera_Forum
Honored Contributor II
768 Views

Hi; 

 

I found in Altera's PCIE core that they use a separate byte enable signal for rx side avalon. This signal is not present in Xilinx's PCIE core. In Altera's PCIE user-guide, I didn't found anything about the validity of byte enable for "completion" TLPs. Only thing mentioned is that these byte enable signals are same as we found in Memory read/write TLPs. But since completion TLPs dont contain any byte enable signals can we safely use that byte enable signal to decode data from completion TLP?? 

 

Thanks
0 Kudos
0 Replies
Reply