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can SGDMA be controlled by FPGA logic?

Altera_Forum
Honored Contributor II
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Dear all,  

 

Can SGDMA be controlled by FPGA logic without any C program from Nios II if we only use it to transfer data between on-chip memory and off-chip memory (DDR2 SDRAM)? 

 

If so, how to do that more easier and efficient? What steps need be done? Anyone has examples/documents? 

 

Thank you very much!
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Altera_Forum
Honored Contributor II
81 Views

You can. 

NIOS does not have a special role, it's just yet another Avalon-MM master. 

 

You can use whatever you want to control SGDMA. All you need is to make your logic an Avalon-MM master which writes the proper values into the SGDMA configuration registers. 

 

So, basically, we're talking about a some kind of state machine. 

That said, slapping in NIOS II/e core and a small C program should be simpler.
Altera_Forum
Honored Contributor II
81 Views

I agree, it's possible but processors are normally more appropriate for control plane type stuff like this.

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