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5988 Discussions

cascading pll with emif core (stratix10)

VMots
Beginner
989 Views

Hello!

I have several emif (ddr4) controllers which everyone have it's own reference clock (from package pin) but I want to feed it from pll when I connect it together and try to implement it I get next error messege (only one is shown):

Error(20181): The permit_cal input port of IOPLL "emif_ed_x7_inst|emif_x32_3|emif_x32_s10_2|arch|arch_inst|pll_inst|pll_inst" is not connected correctly. Enable and export the permit_cal port of downstream IOPLL "emif_ed_x7_inst|emif_x32_3|emif_x32_s10_2|arch|arch_inst|pll_inst|pll_inst" with the Platform Designer GUI and connect to the locked output of upstream IOPLL "u0|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll"

 

but I do not find where to enable this port in the emif ip... 

Can someone help me with this? Or may be advise another solution?

Best regards

 

0 Kudos
13 Replies
VMots
Beginner
977 Views

One more addition: I use Quartus Prime pro 21.2.0

 

sstrell
Honored Contributor III
970 Views

Are you trying to use the core clocks sharing option in the EMIF IP?

VMots
Beginner
854 Views
AdzimZM_Intel
Employee
957 Views

Hi VMots,

 

I'm Adzim. Thank you for using the Intel Community.

 

I've found a KDB for this error message. Link here.

You might need to follow the resolution in there.

 

I think you can enable it in the IOPLL IP under the Cascading tab.

I share the screenshot for that.

AdzimZM_Intel_0-1632976781387.png

 

Please let me know if that helpful.

 

Thanks,

Adzim

VMots
Beginner
853 Views

I am already see this solution but this is not iopll core but the emif core and it need to have permit_cal input. 

sstrell
Honored Contributor III
793 Views

That's for cascading PLLs into each other, not from a PLL to an IP:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/ecpll_d...

 

Simply turn off the cascading option in the PLL parameters and connect the PLL output to the EMIF clock input.  There is no option for a permit_cal input into the EMIF IP because it's not needed.

VMots
Beginner
781 Views

That wasn't a question, how to connect two pll's.

If you have 7 ddr memory controllers in one FPGA it require 14 pins for clock - it is too expensive while one is enough but looks like the intel not give us such possibility.

While you feed ddr memory controllers from plls quartus give you error that you need to connect feedin pll pin with name pll_lock with ddr memory controller pll pin called permit_cal

But permit_cal input is unaccessible from ip configurator

sstrell
Honored Contributor III
716 Views

No, this is where you use the EMIF core clock sharing option I was asking about originally.  You feed the clock to one EMIF and then that EMIF sends the clock to others.  Again, there is no permit_cal pin because it's not part of the IP.  The option you mention is for cascading PLLs (and just PLLs).  From the EMIF parameterization training (https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1122.html):

 

VMots
Beginner
706 Views

you speaking about core clock network sharing this is not that I need...

I need pll reference clock feeding (pll is inside emif core)

AdzimZM_Intel
Employee
723 Views

Hi VMots,


Do you can share the design with me so that I can replicate the error and debug it?


Thanks,

Adzim


VMots
Beginner
677 Views

Hello Adzim!

I can share project archive but it too big to share it here . 

Thank you

Viktor

AdzimZM_Intel
Employee
585 Views

Hi Viktor,


Thanks for sharing the file.

I can see it's the synthesize error.


The Stratix 10 EMIF IP doesn't support PLL cascading as mention in the EMIF User Guide below.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-emi.pd...


I think you have to reconfigure the PLL reference clock that connect to the EMIF IPs.


Regards,

Adzim


AdzimZM_Intel
Employee
474 Views

Hi Viktor,


May I know any update on this?


Regards,

Adzim


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