design example of p-tile avalon-mm ip for pcie for stratix 10 for quartus prime 20.1

[ethanzsq]

I have some questions when I run the example design:

1) Table 2 in user guide shows address and bar map for BAR Interpreter. Dose DMA controller always occupy a single BAR even if I set the size of this BAR larger than 4KB which I notice is the size of DMA controller(0-0xfff)

Resource Address Range           BAR
DMA         0x0 - 0x0FFFF             0
MEM0.s1 0x20000 - 0x27FFF   2
MEM0.s2 0x28000 - 0x2FFFF   2 

2)Should the BAR number of MEM0.s2 change to 4 if I set the total memory size of MEM0 to 64KB? Under such circumstances, Table 2 would be like this?

Resource Address Range           BAR
DMA         0x0 - 0x0FFFF             0
MEM0.s1 0x20000 - 0x2FFFF   2
MEM0.s2 0x30000 - 0x3FFFF   4 

3)Original Table 2 shows that there is no resource belongs to BAR4, but why can I read the configuration space of BAR4?

Thank you very much for your support.

[Rahul_S_Intel1]

Hi ,

 Just confirm your question, do face problem in reading BAR4 address